1. Field of the Invention
The present invention generally relates to semiconductor devices and integrated circuits including metal-oxide-semiconductor field effect transistors (MOSFETs) and, more particularly, to high performance MOSFETs utilizing high-κ gate insulators and metal gates and the formation of low resistance connections thereto.
2. Description of the Prior Art
The desire for increased functionality and increased operating speed of integrated circuits and other electronic devices formed on a semiconductor chip has driven integration density to extreme levels while leading to the development of increasingly sophisticated transistor designs and features in order to preserve and enhance performance as transistors are scaled to smaller sizes. One such design feature is the use of high-κ gate insulators in MOSFETs in order to improve control of the electric field in the transistor channel. However, it has been found that conventional polysilicon gates do not work well with high-κ dielectrics because of transistor threshold voltage pinning Previous publications have claimed this phenomenon is caused by Fermi level pinning effect at the interface between polysilicon and high-κ dielectric. In addition, polyslicon height scaling has been a key technology element to provide parasitic capacitance reduction and gives process space for large angle implantation (such as halo implantation as required for short channel control) as technology node shrinks The doping of scaled polysilicon as a requirement for gate resistance reduction has become very challenging because of the concern about dopant penetration into the transistor channel area. Hence, for the gate electrode, it is generally considered to use a metal, metal alloy or conductive compound of metal such as titanium nitride, hereinafter collectively referred to as simply “metal gate”, rather than polysilicon. The transistor threshold voltage is usually determined or modulated by metal gate work function. The use of a metal gate can provide low gate resistance, enhances the uniformity of the electric field produced in the transistor channel for which the very thin high-κ gate dielectric is also employed. While the metal gate can also be very thin, it is a preferred practice to provide sidewalls on the gate stack to control the location of impurity implantation relative to the gate stack position. Since such sidewalls are typically formed by an isotropic deposition followed by an anisotropic etch, it is generally necessary to provide substantial height for the gate stack to achieve the desired sidewall thickness at the sides to the gate dielectric. It may also be desirable to provide additional structures in the gate stack such as stressed layers to enhance carrier mobility and the like. However, any thickness of the gate electrode approaching the needed gate stack height may alter the transistor threshold voltage and is likely to complicate the etching process for patterning the gate stack. Further, to support accurate formation of very fine and closely spaced conductors, it is generally necessary to develop a highly planar surface by depositing materials which must at least fill, and preferably overfill, the spaces between transistor gate and other structures which also favors design and fabrication of relatively tall gate stacks. As a result, the resistance within the gate stack is generally far higher than may be desired if conventional polysilicon materials or the like are employed to make up the required gate stack height.